Please refer to FIG. 1, which is a circuit diagram showing a circuit of a conventional LLC series resonance converter having synchronous rectification transistors. The LLC series resonance converter 100 in FIG. 1 includes chiefly a switch circuit 110, a resonance circuit 120, a transformer TX, and a full-wave rectification circuit 130.
In the LLC series resonance converter 100, the switch circuit 110 can be a half-bridge circuit including a pair of power transistors S1 and S2 in FIG. 1 and can be a full-bridge circuit as well. Additionally, the resonance circuit 120 includes three resonance parameters connected in series, wherein the parameters are a resonance inductor Ls, a resonance capacitor Cs and a magnetizing inductor Lm of the transformer TX. Of course, for the skilled person, the resonance inductor Ls can be formed from a leakage inductance of the transformer TX, too.
In FIG. 1, the LLC series resonance converter 100 employs the switch circuit 110, the resonance circuit 120, the transformer TX, and the full-wave rectification circuit 130 to convert a DC input voltage Vin of an input terminal into an output voltage Vo of an output terminal, wherein by a suitable parameter design and operating range, the power transistors of the bridge circuit lying to the primary side of the transformer TX can be assured to operate under the condition of zero-voltage switching (ZVS), and rectification transistors lying to the secondary side of the transformer TX can implement zero-current switching (ZCS). From the resonance circuit 120 proper, the three resonance parameters determine two resonance frequencies fs and fin shown in following Equation (1) and Equation (2):fs=1/[2π(Ls·Cs)1/2]  (1)fm=1/{2π[(Ls+Lm)·Cs]}1/2}  (2)
The transformer TX isolates the switch circuit 110 and the resonant circuit 120 from the full-wave rectification circuit 130 by a primary side coil np and two secondary side coils ns1 and ns2 connected in in-phase series. The full-wave rectification circuit 130 includes a pair of synchronous rectification transistors Q1 and Q2 coupled to an output capacitor Co. Sources of the transistors Q1 and Q2 are coupled to a ground terminal of the output voltage Vo. A drain of the transistor Q1 is coupled to an undotted terminal of the secondary side coil ns2, and a drain of the transistor Q2 is coupled to the dotted terminal of the secondary side coil ns1. Additionally, a common connection node between the secondary coils ns1 and ns2 forms a high-voltage terminal of the output voltage Vo.
The power transistors S1 and S2 of the LLC series resonance converter 100 operate at equal pulse width, which is at 50%. A frequency adjustment control circuit 140 is therefore demanded because an adjustment of the output voltage Vo is obtained by changing an operating frequency (switching frequency) f. Additionally, a synchronous rectification driving-signal generating circuit 150 producing suitable gate signals is inserted in the full-wave rectification circuit 130 in order to correctly turn on and turn off the synchronous rectification transistors Q1 and Q2.
Please refer to FIG. 2, which is a waveform diagram showing a time sequence versus waveforms under a condition the operating frequency of the conventional LLC series resonance converter being less than the resonance frequency, wherein the switching frequency f of the transistors (switches) S1 and S2 satisfies the following formula:fh≦f≦fs   (3)
In FIG. 2, an abscissa expresses time, and an ordinate is arranged in four portions. From top to bottom in the given order, the waveforms are voltage waveforms of the two transistors S1 and S2 in the switch circuit 110, current waveforms of a primary side current ir and a magnetizing current im, current waveforms of the two transistors Q1 and Q2 in the full-wave rectification circuit 130, and voltage waveforms of the two transistors Q1 and Q2 in the full-wave rectification circuit 130.
At time of t0, because the primary side current ir is opposite to a reference direction, the power switch S1 is turned on under the ZVS condition. During an interval between t0 and t1, the synchronous rectification transistor Q1 is turned on to have a current, therefore a voltage of the magnetizing inductor Lm is constant and the magnetizing inductor Lm does not take part in the resonance so that the magnetizing current im increases linearly. Due to the resonance between the resonance inductor Ls and the resonance capacitor Cs, the current iQ1 through the synchronous rectification transistor Q1 appears in a quasi-sine waveform.
At time of t1, because the switching period of the working transistor is longer than the resonant period between the resonance inductor Ls and the resonance capacitor Cs, the primary side current ir decreases to be equal to the magnetizing current im before a turn-off of the synchronous rectification transistor Q1 so that the synchronous rectification transistor Q1 should be turned off at this moment. As the resonance capacitor Cs, the resonance inductor Ls and the magnetizing inductor Lm jointly take part in the resonance, for the purpose simplifying analysis, the primary side current ir is regarded as a straight line approximately under the condition of Lm>>Ls supposed.
At time of t2, the transistor S1 is turned off and a body diode of the transistor S2 is turned on. At time of t3, a voltage of the transistor S1 drops to a voltage of the body diode, and the transistor S2 is turned on under ZVS condition. During intervals from t3 to t4 and from t4 to t5, similar operating processes can be analyzed out. The operating statuses and the current waveform iQ2 similar to the synchronous rectification transistor Q1 also occur to the synchronous rectification transistor Q2. The currents iQ1 and iQ2 compose an output rectification current irec. During the interval between t1 and t2 or between t4 and t5, because the current of the synchronous rectification transistors Q1 or Q2 decreases to zero, which always happens before the synchronous rectification transistor S1 or S2 is turned off, conducting pulse widths for the synchronous rectification transistors Q1 and Q2 are smaller than conducting pulse widths for the transistors S1 and S2.
In FIG. 2, driving pulses of the synchronous rectification transistors Q1 and Q2 have to be off when the currents (flowing from the sources to the drains) decrease to zero, that is, are off during the dead time (t1˜t2) of the irec. Otherwise, the phenomena occur that the synchronous rectification transistors Q1 and Q2 are turned on at the same time and the secondary coils ns1 and ns2 short-circuit, so that the circuit would not be able to operate properly and safely. Accordingly, the driving signals of the synchronous rectification transistors Q1 and Q2 cannot be simply obtained from the driving signals of the power switches S1 and S2, and neither can be obtained from the coils of the transformer TX.
When the LLC series resonance converter 100 operates at a frequency f greater than the resonance frequency fs, the dead area of the output rectification current irec, that is, the time interval both the synchronous rectification transistors Q1 and Q2 are turned off, will disappear. Under this condition, the output rectification current irec has a quasi-sine absolute value waveform, and the driving pulses of the synchronous rectification transistors Q1 and Q2 are synchronous with the driving pulses of the corresponding switches S1 and S2, as shown in FIG. 3. Additionally, when the LLC series resonance converter 100 operates at the frequency f greater than the resonance frequency fs, the dead area of the above-mentioned irec become zero and the driving signals of the synchronous rectification transistors Q1 and Q2 can be simply obtained from the driving signals of the power switches S1 and S2 lying in the primary side.
Please refer to FIG. 4, which is a circuit diagram showing a conventional synchronous rectification scheme of the conventional LLC series resonance converter. In FIG. 4 and FIG. 1, identical circuit devices are given identical graphical symbols. Additionally, at least a synchronous circuit 410, a constant width pulse generator 420, and an AND gate 430 are further installed in the LLC series resonance converter 400.
In FIG. 4, when the switching frequency of the transistors S1 and S2 is less than the resonance frequency fs, the constant width pulse generator 420 produces a synchronous rectification driving signal, a pulse width of which is determined by the resonance parameters Ls and Cs, and a rising edge of which is synchronized with a rising edge of a synchronous signal VSYN by the synchronous circuit 410. The synchronous signal VSYN can be a voltage signal of a secondary side coil of the transformer TX, can be a driving signal of high-side or low-side power device lying in one arm of the half-bridge or fall-bridge switch circuit as well, and of course can be also obtained by detecting a conducting voltage across a body diode of a synchronous rectification transistor.
When the switching frequency f is greater than the resonance frequency fs, the driving signals the synchronous rectification transistors Q1 and Q2 are synchronized with the driving signals of the transistors S1 and S2. The constant width pulse signal VFOT and the driving signal Vg of the transistor S1 (or S2) processed by the AND gate 430 to obtain the synchronous rectification driving signal complete.
The advantage of the scheme in FIG. 4 is that the circuit is simple and only requires one synchronous circuit 410 and one constant width pulse generator 420. But the disadvantage is that the adaptive ability is insufficient and the driving pulse width cannot be adjusted automatically in accordance with the variance of the circuit parameters so that the best control of the synchronous rectification transistors cannot be achieved.
Please refer to FIG. 5, which is a circuit diagram showing another conventional synchronous rectification scheme of the conventional LLC series resonance converter. In FIG. 5 and FIG. 1, identical circuit devices are given identical graphical symbols. Additionally, it is known by comparing FIG. 5 and FIG. 4 that the AND gate is removed from the LLC series resonance converter 500 but a comparator 510 and an OR gate 520 are installed in addition to.
In FIG. 5, when a current flows through the drain and the source of the synchronous rectification transistor, a channel resistance of which causes a voltage drop to be generated across. The voltage drop Vds(on) and a constant reference voltage Vref are compared by the comparator 510 to produce a pulse signal Vcom. In a state of a light load, as the voltage drop Vds(on) is very small, a comparing signal is difficult to be obtained so that the constant width pulse VFOT is produced by the synchronous circuit 410 and the constant width pulse generator 420 the same as FIG. 4. The constant width pulse signal VFOT and the pulse signal Vcom are processed by the OR gate 520 to obtain the complete synchronous rectification driving signal.
The advantage of the scheme in FIG. 5 is that the driving pulses of the synchronous rectification transistors can be obtained adaptively. However, the amplitude of the voltage Vds(on) is very low. In order to accomplish the best synchronous rectification effect, the reference voltage Vref has to be very low so that the voltage Vds(on) is very easily influenced by disturbance. Particularly, when the LLC circuit operates in states of a light load, starting, a dynamic load, or a protection -circuit working, as the voltage Vds(on) has oscillation or is disturbed, the output signal Vcom of the comparator 510 appears an error signal, and if the error signal is serious, the synchronous rectification transistors will have a common short-circuit phenomenon.